Sharp Pocket Computer 1360 - Competence Center
Language Machine Quick Manual for the Sharp PC-1360
Sharp PC-1360 has a SC61860 CPU
Machine Language (ML) is the one of this CPU, that's obvious but still useful to be said. The interesting point then, is that
this quick manual is also working for all the Sharp Pocket Computers of the 80's and early 90's, from the Sharp PC-1245 to the Sharp PC-1475 as far as I know. Need I to say but the SC61860 is an 8 bits processor, based on the CMOS technology. It has a ROM of 136 Kb and works at a frequency of 768 kHz.
Notice : almost all numbers will be given in hexadecimal format. The numbers in hexadecimal will be preceeded with a & sign, to distinguish them from decimal numbers. For example : &3F (hexadecimal) is equal to 63 (decimal).
Registers and Internal RAM
CPU Registers
External storage pointersThere are two 16 bits pointer registers to address external storage space, PC and DP.
PC is so called Program Counter.
DP is for general use and stands for Data Pointer.
Internal RAM pointerP, Q and R are internal RAM pointers. Internal RAM consists of only 96 bytes and it would be enough for these pointer registers to be 6 bits. However P, Q and R are 7 bits long registers.
P and Q are for general use and R is the stack pointer.
Arithmetic registersThere are two 16 bits registers, X and Y. Their low and high bytes are distinguished with XL, XH, YL and YH.
There are two 8 bits accumulators, A and B.
There are two 8 bits index pointers, I and J. We should also talk about the 8 bits D register as an index pointer. This is an internally used pointer by the CPU in some machine language instructions.
There are four 8 bits general pointers, K, L, M and N.
Internal RAM
CPU has 96 bytes internal RAM space. CPU registers are mapped in this space. For example accumulator A is located &02 of internal RAM. System stack and some I/O ports are also here. Internal RAM is faster and more convenient than external RAM. Databus is 8 bits wide.
| Register | Internal RAM address | Description Notes |
| P | | 7 bits Internal RAM pointer |
| Q | 7 bits Internal RAM pointer |
| R | 7 bits Internal RAM stack pointer |
| PC | 16 bits Program Counter |
| DP | 16 bits Data Pointer |
| Z | Zero Flag |
| C | Carry Flag |
| D | Internal Index (not accessible to user) |
| I | &00 | Index |
| J | &01 | Index |
| A | &02 | Main Accumulator |
| B | &03 | Secondary Accumulator |
| XL | &04 | X = XL + 256 x XH |
| XH | &05 |
| YL | &06 | Y = YL + 256 x YH |
| YH | &07 |
| K | &08 | General use |
| L | &09 | General use |
| M | &0A | General use |
| N | &0B | General use |
| | &0C - &5B | System Stack (starts at &5B and increases downwards) |
| IA | &5C | I/O port A |
| IB | &5D | I/O port B |
| FO | &5E | I/O port F |
| OUTC | &5F | Control Port |
External Storage Space
External storage space is a 64 Kb linear address space of &0000 - &FFFF. The first 8 Kb area (&0000 - &2000) of this space is called "internal ROM" which is only accessible via PC (You cannot read nor write using DP). Program codes and many kinds of data are stored in external storage.
The SC61860 Set of Instructions (opcodes)
The CPU has more than 100 instructions in machine language. As you can guess, one byte is enough to set an instruction in machine language (or operation code), since a byte allows to have up to 256 instructions and there are only about 100 instructions. The instructions can be classified according to the number of bytes they will use :
- one byte long : they require only an operation code of 8 bits that is the instruction for the CPU. The LP instruction is the only exception to this rule. 2 bits of the LP are the operation code and 6 bits are the parameter of this operation code.
- two bytes long : they require an operation code of 8 bits and a parameter of 8 bits. The CAL instruction is the only exception to this rule. 3 bits are used for the operation code and 13 bits for the parameter.
- three bytes long : they require an operation code of 8 bits and one parameter of 16 bits. The two last bytes are the Low Byte (LB) and the High Byte (HB) of the 16 bits parameter (PARAM = LB + 256 x HB)
- more than three bytes long : they require an operation code of 8 bits and more parameters of 8 or 16 bits. For example, they are used for table jumps .
Notices :- All registers between brackets stand for the content of the address memorized in this register. We commonly say that this register is a pointer to the content of an address. For example if A = 49201. Then [A] points to the content of address 49201 which may hold any value between 0 and 255 (since we are dealing with an 8 bits computer).
- D pointer will be written d in order to help you remember that you cannot use it, it is an internal pointer managed by the CPU for some instructions.
- BCD in some instructions stands for Binary Coded Decimal. This is the way that Sharp managed to encode real numbers in their PCs. Since the CPU is an 8 bits CPU, Sharp wisely created a set of ML instructions for managing directly real numbers.
Hex Dec Instruction Function Bytes Cycles Flags
&00 000 LII n n -> I 2 4
&01 001 LIJ n n -> J 2 4
&02 002 LIA n n -> A 2 4
&03 003 LIB n n -> B 2 4
&04 004 IX X + 1 -> X l 6
X -> DP
&05 005 DX X - 1 -> X 1 6
X -> DP
&06 006 IY Y + 1 -> Y 1 6
Y -> DP
&07 007 DY Y - 1 -> Y 1 6
Y -> DP
&08 008 MVW I -> d 1 5+2xd
repeat
[Q] -> [P]
P + 1 -> P
Q + 1 -> Q
d - 1 -> d
until d=FF
&09 009 EXW I -> d 1 6+3xd
repeat
[P] <-> [Q]
P + 1 -> P
Q + 1 -> Q
d - 1 -> d
until d=FF
&0A 010 MVB J -> d 1 5+2xd
repeat
[Q] -> [P]
P + 1 -> P
Q + 1 -> Q
d - 1 -> d
until d=FF
&0B 011 EXB J -> d 1 6+3xd
repeat
[P] <-> [Q]
P + 1 -> P
Q + 1 -> Q
d - 1 -> d
until d=FF
&0C 012 ADN I -> d 1 7+3xd C,Z
repeat
[P] + A -> [P] (BCD)
P - 1 -> P
d - 1 -> d
until d=FF
&0D 013 SBN I -> d 1 7+3xd C,Z
repeat
[P] - A -> [P] (BCD)
P - 1 -> P
d - 1 -> d
until d=FF
&0E 014 ADW I -> d 1 7+3xd C,Z
repeat
[P] + [Q] -> [P] (BCD)
P - 1 -> P
Q - 1 -> Q
d - 1 -> d
until d=FF
&0F 015 SBW I -> d 1 7+3xd C,Z
repeat
[P] - [Q] -> [P] (BCD)
P - 1 -> P
Q - 1 -> Q
d - 1 -> d
until d=FF
&10 016 LIDP nm n -> DPH ; m -> DPL 3 8
&11 017 LIDL n n -> DPL 2 5
&12 018 LIP n n -> P 2 4
&13 019 LIQ n n -> Q 2 4
&14 020 ADB [P+1,P] + (B,A) -> [P+1,P] 1 5 C,Z
P + 1 -> P
&15 021 SBB [P+1,P] - (B,A)-> [P+1,P] 1 5 C,Z
P + 1 -> P
&18 024 MVWB I -> d l 5+4xd
repeat
[DP] -> [P]
P + 1 -> P
DP + 1 -> DP
d - 1 -> d
until d=FF
&19 025 EXWD I -> d 1 7+6xd
repeat
[DP] <-> [P]
P + 1 -> P
DP + 1 -> DP
d - 1 -> d
until d=FF
&1A 026 MVBD J -> d 1 5+4xd
repeat
[DP] -> [P]
P + 1 -> P
DP + 1 -> DP
d - 1 -> d
until d=FF
&1B 027 EXBD J -> d 1 7+6xd
repeat
[DP] <-> [P]
P + 1 -> P
Q + 1 -> Q
d - 1 -> d
until d=FF
&1C 028 SRW I -> d 1 5+1xd
repeat
[P] <- 4 bit shift right
P - 1 -> P
d - 1 -> d
until d=FF
&1D 029 SLW I -> d 1 5+1xd
repeat
[P] <- 4 bit shift left
P - 1 -> P
d - 1 -> d
until d=FF
&1E 030 FILM I -> d 1 5+1xd
repeat
A -> [P]
P + 1 -> P
d - 1 -> d
until d=FF
&1F 031 FILD I -> d 1 4+3xd
repeat
A -> [DP]
DP + 1 -> DP
d - 1 -> d
until d=FF
&20 032 LDP P -> A 1 2
&21 033 LDQ Q -> A 1 2
&22 034 LDR R -> A 1 2
&23 035 RA 0 -> A 1 2
&24 036 IXL X + 1 -> X 1 7
X -> DP
[DP] -> A
&25 037 DXL X - 1 -> X 1 7
X -> DP
[DP] -> A
&26 038 IYS Y + 1 -> Y 1 6
Y -> DP
A -> [DP]
&27 039 DYS Y - 1 -> Y 1 6
Y -> DP
A -> [DP]
&28 040 JRNZP n if Z=0 2 7/4
then PC + 1 + n -> PC
else PC + 2 -> PC
&29 041 JRNZM n if Z=0 2 7/4
then PC + 1 - n -> PC
else PC + 2 -> PC
&2A 042 JRNCP n if C=0 2 7/4
then PC + 1 + n -> PC
else PC + 2 -> PC
&2B 043 JRNCM n if C=0 2 7/4
PC + 1 - n -> PC
else PC + 2 -> PC
&2C 044 JRP n PC + 1 + n -> PC 2 7
&2D 045 JRM n PC + 1 - n -> PC 2 7
&2F 047 LOOP n [R] - 1 -> [R] 2 10/7
if C=0
then PC + 1 - n -> PC
else PC + 2 -> PC
&30 048 STP A -> P 1 2
&31 049 STQ A -> Q 1 2
&32 050 STR A -> R 1 2
&34 052 PUSH R - 1 -> R 1 3
A -> [R]
&35 053 DATA I -> d l 11+4xd
repeat
(B,A) -> [P]
P + 1 -> P
(B,A) + 1 -> (B,A)
d - 1 -> d
until d=FF
&37 055 RTN [R,R+1] -> PC l 4
R + 2 -> R
&38 056 JRZP n if Z=1 2 7/4
then PC + 1 + n -> PC
else PC + 2 -> PC
&39 057 JRZM n if Z=1 2 7/4
then PC + 1 - n -> PC
else PC + 2 -> PC
&3A 058 JRCP if C=1 2 7/4
then PC + 1 + n -> PC
else PC + 2 -> PC
&3B 059 JRCM if C=1 2 7/4
then PC + 1 - n -> PC
else PC + 2 -> PC
&40 064 INCI I + 1 -> I 1 4 C,Z
&41 065 DECI I - 1 -> I l 4 C,Z
&42 066 INCA A + 1 -> A l 4 C,Z
&43 067 DECA A - 1 -> A 1 4 C,Z
&44 068 ADM [P] + A -> [P] l 3 C,Z
&45 069 SBM [P] - A -> [P] 1 3 C,Z
&46 070 ANMA [P] and A -> [P] 1 3 Z
&47 071 0RMA [P] or A -> [P] 1 3 Z
&48 072 INCK K + 1 -> K 1 4 C,Z
&49 073 DECK K - 1 -> K 1 4 C,Z
&4A 074 INCM M + 1 -> M l 4 C,Z
&4B 075 DECM M - 1 -> M 1 4 C,Z
&4C 076 INA IA-Port -> A 1 2
&4D 077 NOPW No Operation l 2
&4E 078 WAIT n No Operation 2 6+n
&4F 079 WAITI No Operation 1 5+4xd
&50 080 INCP P + 1 -> P l 2 C,Z
&51 081 DECP P - 1 -> P l 2 C,Z
&52 082 STD A -> [DP] 1 2
&53 083 MVDM [P] -> [DP] 1 3
&54 084 READM [PC+1] -> [P] 1 3
&55 085 MVMD [DP] -> [P] l 3
&56 086 READ [PC+1] -> A 1 3
&57 087 LDD [DP] -> A 1 3
&58 088 SWP A <- swap bits [1-4]<->[5-8] 1 2
&59 089 LDM [P] -> A 1 2
&5A 090 SL A <- 1 bit shift left 1 2 C
&5B 091 POP [R] -> A 1 2
R + 1 -> R
&5D 093 OUTA [5C] -> IA-Port 1 3
&5F 095 0UTF [5E] -> FO-Port l 3
&60 096 ANIM n [P] and n -> [P] 2 4 Z
&61 097 ORIM n [P] or n -> [P] 2 4 Z
&62 098 TSIM n [P] and n -> Z 2 4
&63 099 CPIM n [P] - n -> C,Z 2 4 C,Z
&64 100 ANIA n A and n -> A 2 4 Z
&65 101 ORIA n A or n -> A 2 4 Z
&66 102 TSIA n A and n -> Z 2 4
&67 103 CPIA n A - n -> C,Z 2 4 C,Z
&69 105 DTJ Do Table Jump - -
&6B 107 TEST n n -> TEST 2 4 Z
&70 112 ADIM n [P] + n -> [P] 2 4 C,Z
&71 113 SBIM n [P] - n -> [P] 2 4 C,Z
&74 116 ADIA n A + n -> A 2 4 C,Z
&75 117 SBIA n A - n -> A 2 4 C,Z
&78 120 CALL nm PC + 3 -> [R-1,R-2] 3 8
R - 2 -> R
nm -> PC
&79 121 JP nm nm -> PC 3 6
&7A 122 PTJ Prepare Table Jump 4 9
&7C 124 JPNZ nm if Z=0 3 6
then nm -> PC
else PC + 3 -> PC
&7D 125 JPNC nm if C=0 3 6
then nm -> PC
else PC + 3 -> PC
&7E 126 JPZ nm if Z=1 3 6
then nm -> PC
else PC + 3 -> PC
&7F 127 JPC nm if C=1 3 6
then nm -> PC
else PC + 3 -> PC
&80 128 LP l l -> P 1 2
+l +l (1 = &00 to &3F)
&C0 192 INCJ J + 1 -> J 1 4 C,Z
&C1 193 DECJ J - 1 -> J 1 4 C,Z
&C2 194 INCB B + 1 -> B 1 4 C,Z
&C3 195 DECB B - 1 -> B 1 4 C,Z
&C4 196 ADCM [P] + A + C -> [P] 1 3 C,Z
&C5 197 SBCM [P] - A - C -> [P] 1 3 C,Z
&C6 198 TSMA [P] and A -> Z 1 3
&C7 199 CPMA [P] - A -> C,Z 1 3 C,Z
&C8 200 INCL L + 1 -> L 1 4 C,Z
&C9 201 DECL L - 1 -> L 1 4 C,Z
&CA 202 INCN N + 1 -> N 1 4 C,Z
&CB 203 DECN N - 1 -> N 1 4 C,Z
&CC 204 INB IB-Port -> A 1 2
&CE 206 NOPT No Operation 1 3
&D0 208 SC 1 -> C 1 2 C,Z
1 -> Z
&D1 209 RC 0 -> C 1 2 C,Z
1 -> Z
&D2 210 SR A <- 1 bit shift right 1 2 C
&D4 212 ANID n [DP] and n -> [DP] 2 6 Z
&D5 213 ORID n [DP] or n -> [DP] 2 6 Z
&D6 214 TSID n [DP] and n -> Z 2 6
&D8 216 LEAVE 0 -> [R] 1 2
&DA 218 EXAB A <-> B 1 3
&DB 219 EXAM A <-> [P] 1 3
&DD 221 0UTB [5D] -> IB-Port 1 2
&DF 223 0UTC [5F] -> Control Port 1 2
&EO 224 CAL ln PC + 2 -> [R-1,R-2] 2 7
+l +l R - 2 -> R
ln -> PC |
How to include Machine Language programs in the PC memory and in Basic programs
Where to put Machine Language programs ?
The problem here is that ML programs can be put anywhere in the RAM space with the risk of getting in conflict with Basic space. To understand that point, here is the memory organization within a RAM card :
In this standard configuration, there are two ways for including your ML programs :
- Put the ML routine in the Basic programs area : this is quite complicated to do because you have to input a REM line that includes as many characters as your ML program has bytes, find the RAM address where the REM line starts and finally POKE ML data into this REM line.
- Put the ML routine in the Free space area : the risk is then that your ML program erases part of your Basic programs or your variables, or gets erased by them. In this case, you also have to deal with finding RAM addresses.
Hopefully, there is a smart way to bypass the problems encountered in the two standard ways of putting ML programs in the RAM space. The idea is put on the following picture :
Did you get it ? The idea is to dedicate a memory space of the RAM card to place your ML programs. The only side effect to this way of doing is that
setting up this memory organization will delete all of your data stored in the RAM card. So, make sure to save all you Basic programs to a tape or a big PC before proceeding. Also be careful that your Basic free space will decrease porportionally to the space that you will dedicate to ML programs. Here is how you should proceed :
First, you will have to know the Start address and End address of the Basic + variables space. These addresses change according to the size of your RAM card that is placed in slot #1.
| RAM Card | Start Address of Basic | End Address of Basic |
|---|
| 8 Kb | &E030 | &F9C9 |
|---|
| 16 Kb | &C030 | &F9C9 |
|---|
| 32 Kb | &8030 | &F9C9 |
|---|
Be careful : this table only applies to Sharp PC-1360, for other Sharp PCs, please contact me. I will be very happy to give the information of this table according to your PC model.
Now, to the Start Address of Basic found from the above table, you will add the amount of bytes that you want to dedicate to ML.
For example, if you want to dedicate 2 Kb (2 * 1024 = 2048 bytes = &800 bytes) on a 16 Kb card, you will calculate : ADR = &C030 + &800 = &C830. Make sure that this number remains smaller than the End Address of Basic as put in the above table. Note that ADR is made of a Low Byte and a High Byte, with ADR = LB + 256 x HB. In our example LB = &30 and HB = &C8.
And now, only a few more steps to execute :
- All Reset your Sharp PC, answer Y to confirm
- write POKE &FFD7, LB, HB (ADR = LB + 256 x HB), press ENTER to validate line
- Press MODE key to enter PRO mode
- write NEW, press ENTER to validate command
- Press MODE key again to go back to RUN mode
It is done, you have a free space for you ML programs. Write down the range of RAM addresses in which this space is :
- Old Start Basic Address (&C030 in our example)
- New Start Basic Address - 1 (&C82F = &C830 - 1 in our example)
A first ML program
We will create a very simple program : our LM program will just add two 8 bits numbers (ranging from 0 to 255).
Our ML program will look like this (the addresses are given as an example, they should be adapted as explained in the above paragraph) :
| Address | Machine Language | Hexadecimal Coding | Explanation |
|---|
| &C900 | - | - | First number that will be given by Basic program |
|---|
| &C901 | - | - | Second number that will be given by Basic program |
|---|
| &C902 | - | - | Result of the addition of the two numbers |
|---|
| &C903 | LIDP C900 | &10 &C9 &00 | &C900 -> DP, DP points to first number address |
|---|
| &C906 | LDD | &57 | [DP] -> A, A receives value of first number |
|---|
| &C907 | LP 03 | &83 | &03 -> P, P receives value &03 and points to B register |
|---|
| &C908 | EXAB | &DA | A <-> B, A and B registers are swapped, B now contains value of first number |
|---|
| &C909 | LIDL 01 | &11 &01 | &01 -> [DP low byte], DP now points to second number address |
|---|
| &C90B | LDD | &57 | [DP] -> A, A receives value of second number |
|---|
| &C90C | ADM | &44 | [P] + A -> [P], A and B are added and B receives the result of the addition |
|---|
| &C90D | EXAB | &DA | A <-> B, A and B registers are swapped, A now contains the result of the addition |
|---|
| &C90E | LIDL 02 | &11 &02 | &02 -> [DP low byte], DP now points to Result address |
|---|
| &C910 | STD | &52 | A -> [DP], Result receives its value |
|---|
| &C911 | RTN | &37 | Return, exits from ML program and goes back to Basic |
|---|
The Basic program that will use this ML program looks like this :
10 CLS : WAIT 0
20 POKE &C903, &10, &C9, &00, &57, &83, &DA, &11, &01, &57, &44, &DA, &11, &02, &52, &37
30 INPUT "First Number = "; A
40 INPUT "Second Number = "; B
50 POKE &C900, A, B : CALL &C903
60 PRINT "Sum = ", PEEK &C902
70 END |
This is quite a fastidious way of writing ML programs, isn't it? This is how things had to be done... until I wrote the
PockASM compiler only 2 years ago. This is how the previous program will look in PockASM:
ORG &C900
B_REG EQU 3
NUM1: DB 0 # First number that will be given by Basic program
NUM2: DB 0 # Second number that will be given by Basic program
RESULT: DB 0 # Result of the addition of the two numbers
LIDP NUM1 # DP points to first number address
LDD # A receives value of first number
LP B_REG # P points to B register
EXAB # A and B are swapped, B contains first number value
LIDL LB@NUM2 # DP now points to second number address
LDD # A receives value of second number
ADM # A and B are added, B receives the result of the addition
EXAB # A and B are swapped, A contains the result of the addition
LIDL LB@RESULT # DP now points to Result address
STD # Result receives its value
RTN # Return, exits from ML program and goes back to Basic |
This is much easier to read, don't you believe so?
I. aldweb
Manuel rapide sur la CPU du Sharp PC-1360 et son Langage Machine
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